The present invention will be described with an example application for an Ethernet computer network peripheral device which couples a host computer system to a network of computers. In this example application, the Ethernet computer network peripheral device updates a set of registers with new statistical data regarding transmission or reception of data packets over the network of computers, and the host computer system accesses such a set of registers for reading such statistical data. However, from this example application, it should be appreciated by one of ordinary skill in the art of electronic systems design that the present invention may be used for other applications requiring coordination of access to a set of registers by any type of computer peripheral device and a host system.
Referring to FIG. 1, a computer peripheral device 102 may be an Ethernet computer network peripheral device which allows a host computer 104 to communicate with other computers within a network of computers 106. Such a computer peripheral device 102 receives and transmits data packets via the network of computers 106. The computer peripheral device 102, which may be an Ethernet computer network peripheral device, receives and transmits data packets on the network of computers 106 in accordance with standard data communications protocols such as the IEEE 802.3 network standard or the DIX Ethernet standard as is commonly known to one of ordinary skill in the art of Ethernet computer network peripheral device design.
An example Ethernet computer network peripheral device 102 which operates according to the IEEE 802.3 network standard is described in a copending U.S. patent application entitled Mechanism for Run Time Programming of Hardware Resources with Least Interference with Continued Operation having Ser. No. 09/244431 and Filing Date Feb. 4, 1999 and having common assignee herewith. This patent application with Ser. No. 09/244431 is incorporated herewith by reference.
The host computer 104 may be a PC or any other type of computer, and has a host system which includes a CPU 108. The CPU 108 further processes a data packet received from the network of computers 106 or generates a data packet to be transmitted on the network of computers 106. A bus interface 110 is disposed between the CPU 108 and the peripheral device 102, and data is exchanged between the peripheral device 102 and the CPU 108 via the bus interface 110.
As discussed in U.S. patent application with Ser. No. 09/244431 referring to FIG. 2, the computer network peripheral device 102 has a peripheral device function module 202 for transmitting and receiving data packets via the network of computers 106. The peripheral device function module 202 is also referred to as a transmit control block for transmission of data packets via the network of computers 106 and as a receive control block for reception of data packets over the network of computers 106. The peripheral device function module 202 may be implemented with any type of data processing device.
The peripheral device function module 202 runs on a peripheral device clock 204. In some computer network peripheral devices, the peripheral device clock 204 may be from the network of computers 106 and typically runs at 25 MHZ (megahertz) or 2.5 MHZ (megahertz), depending on the rate of data transmission or reception over the network of computers 106. In addition, the peripheral device clock 204 may be stopped if the network of computers 106 is inoperative or if the connector that couples the peripheral device function module 202 to the clock of the network of computers 106 is unplugged.
When the peripheral device function module 202 transmits or receives data packets over the network of computers 106, the peripheral device function module 202 updates a statistics module 206. The statistics module 206 keeps track of statistical data regarding transmission and reception of data packets over the network of computers 106 in a set of data registers 208. Such statistical data may be related to the number of data packets transmitted or received within a given time period, or the number of different type of errors such as dribbling bit errors, frame check sequence errors, etc. as known to one of ordinary skill in the art of computer network peripheral device design.
The statistics module 206 may further be implemented with incrementers, adders, or any other type of data processing elements known to one of ordinary skill in the art of digital systems design for updating the data registers 208. The data registers 208 may be implemented with typical data registers or any other type of date storage elements as known to one of ordinary skill in the art of digital systems design.
The CPU 108 of the host system 104 also accesses the statistics module 206 for reading the statistical data stored in the data registers 208 via the bus interface 110. The bus interface 110 runs on a bus clock 210. The bus clock 210 is typically the clock for running the host system 104, and typically has a nominal frequency of 33 MHZ or 25 MHZ. However, because the host system 104 also has power saving features, the bus clock may vary from the nominal frequency down to zero Hz. For example, the source of the bus clock 210 may not be running if the host system 104 is in a power savings mode as known to one of ordinary skill in the art of computer systems design.
However, even when the bus clock 210 is not running, the peripheral device function module 202 needs to update the statistics module 206. Thus, the statistics module 206 cannot run on the bus clock 210. Alternatively, even when the peripheral device clock 204 is inoperative, the bus interface 110 needs to be able to access the statistics module 206 to read statistics data from the data registers 208. Thus, the statistics module 206 cannot run on the peripheral device clock 204.
Thus, the statistics module 206 runs on an independent clock 212 disposed within the statistics module 206. In addition, a handshaking mechanism for synchronizing to the peripheral device clock 204 and to the independent clock 212 is desired when the peripheral device function module 202 has new statistical data for updating the statistics module 206. Furthermore, a handshaking mechanism for synchronizing to the peripheral device clock 204, to the bus clock 210, and to the independent clock 212, is desired when the peripheral device function module 202 has new statistical data for updating the statistics module 206 and when the bus interface 110 requests access to read the data registers 208.